1. Field of the Invention
The present invention relates to a transistor output circuit using an insulated gate transistor and, more particularly, to a transistor output circuit which prevents the oscillation (to be referred to as ringing hereinafter) of an output signal.
2. Related Background Art
FIG. 4 is a circuit diagram showing a prior art CMOS output circuit. Referring to FIG. 4, the CMOS output circuit includes a P-channel MOS transistor (to be referred to as a PMOS transistor hereinafter) M1, and an N-channel MOS transistor (to be referred to as an NMOS transistor hereinafter) M2. The source electrode, the drain electrode, and the gate electrode of the NMOS transistor M2 are connected to a GND terminal 2, an output terminal 4, and an input terminal 3, respectively. The source electrode, the drain electrode, and the gate electrode of the PMOS transistor M1 are connected to a power supply 1, the output terminal 4, and the input terminal 3, respectively. Upon application of a logic level to the input terminal 3, the inverted logic level is output from the output terminal 4.
In recent years, a strong demand for driving a large capacitive load with a high-speed signal such as a video signal has arisen. To drive a large capacitive load by a CMOS output circuit, the output impedance of the CMOS output circuit must be lowered. For this purpose, the ratio (W/L) of the gate width (W) to the gate length (L) of each of the PMOS and NMOS transistors M1 and M2 must be increased.
However, because of the parasitic inductance in the line from the output terminal to the capacitive load of the CMOS output circuit, or the power supply line of the CMOS output circuit, a closed circuit consisting of L, C, and R is equivalently formed, as shown in FIG. 5 (R equivalently represents the output impedance of the CMOS output circuit, L equivalently represents the inductance of the power supply (V.sub.DD) line or the line from the output terminal to the capacitive load, and C represents the capacitive load). For this reason, the output voltage waveform which appears in the capacitive load oscillates at a frequency f given by equation (1) below. Since Q of the oscillation is inversely proportional to R, the oscillation is harder to attenuate as the output impedance of the CMOS output circuit is lowered: ##EQU1##
In a system for processing information at a high speed, if this ringing becomes large, information (voltage) may be erroneously transmitted, and additionally, unnecessary radiation caused by radio waves may increase.
When the capacitive load is to be driven at a high speed by the prior art CMOS output circuit, large ringing inevitably occurs, as described above.